Cache-Oblivious Sparse Matrix--Vector Multiplication by Using Sparse Matrix Partitioning Methods

In this article, we introduce a cache-oblivious method for sparse matrix vector multiplication. Our method attempts to permute the rows and columns of the input matrix using a hypergraph-based sparse matrix partitioning scheme so that the resulting matrix induces cache-friendly behaviour during sparse matrix vector multiplication. Matrices are assumed to be stored in row-major format, by means of the compressed row storage (CRS) or its variants incremental CRS and zig-zag CRS. The zig-zag CRS data structure is shown to t well with the hypergraph metric used in partitioning sparse matrices for the purpose of parallel computation. We present the separated block-diagonal (SBD) form as the appropriate matrix structure for cache enhancement. We use a k-way set-associative idealised cache model, and we have implemented a run-time cache simulation library enabling us to analyse cache behaviour for arbitrary matrices and arbitrary cache properties during matrix vector multiplication within this model. The results of these simulations are then veri ed by actual experiments run on various cache architectures. In all these experiments, we use the Mondriaan sparse matrix partitioner in one-dimensional mode. The savings in computation time achieved by our matrix reorderings reach up to 50 percent, in case of a large link matrix.